Integrated circuits include a plurality of electronic devices including transistors, diodes, resistors, capacitors, etc. These devices can be fabricated in a substrate and connected to each other using conductors that may also be fabricated in the substrate. It is generally desirable to reduce the size of integrated circuits to allow for smaller packages, as well as to reduce power consumption and improve high frequency operation.
It is well known that current complementary metal oxide semiconductor (CMOS) technology faces many scaling challenges in order to continue to provide reliable, fast, miniaturized electronic circuitry. For example, lithographic patterning of transistor features is approaching the limits of its capabilities. In addition, CMOS processing is costly and time consuming, often requiring over 200 fabrication steps and 30 or more photolithographic mask steps.
Floating gate (FG) transistors are commonly employed in FLASH memory in electronic systems. Since FG transistors are fabricated using CMOS processing, they face the same technological challenges as CMOS transistors, as well as additional challenges such as increased lateral parasitic capacitance and reduced charge sensitivity.
In devices that include capacitors, small size capacitors with high capacitance values are difficult to fabricate because of the relatively low dielectric constant (k) of the dielectric materials currently used. To reduce the capacitor size for a given dielectric, both the capacitor plate size and the distance (d) between plates can be proportionally scaled down. While the former quantity is in principle limited only by the technical capabilities of the current lithographic techniques, attempts to reduce the distance d must take into account the increased possibility of an electrical breakdown.
A highly conductive quasi two-dimensional electron gas (q2DEG), based on interface polarity discontinuities has been reported in both semiconducting and oxide insulating multilayer structures. It has been further shown that an external electric field can control the conductance of the q2DEG. A reconfigurable electric circuitry approach based on q2DEG patterns defined by local ferroelectric polarization has been described in U.S. patent application Ser. No. 11/749,368, which is hereby incorporated by reference.